SE Aspen microprocessor - Qualcomm MSM 7227 RISC cpu with embedded DSP

Yes, today on Sony Ericsson Aspen again. The microprocessor for M1i device using a Qualcomm chip, with 600MHz clock speed, with a lot of embedded DSP. Summarize of the specification of this CPU:

Type: MSM7227
Manufacturer: Qualcomm
Year Released: 2009
Predecessor: Qualcomm MSM 7225 (528MHz clock speed, 32 bit)
Instructions Sets: ARMv6
CPU Core: ARM11
Features: Embedded 320MHz DSP (GSM quad band, GPRS / EGPRS multislot Class 12, EDGE, UMTS Release 6, 7.2Mbps HSDPA, HSUPA 5.76 Mbps, MBMS baseband), 400MHz modem processor.

As this chip release in 2009, so this is one generation behind of current powerful Qualcomm Snapdragon cpu chip. What MSM stand for? Okay, it acronym for Mobile Station Modem, it a platform chipset solution that enable cost-effective mobile handsets with advanced capabilities that leverage 3G technology.

If you would like to further find out list of all phone (or smartphone) that using MSM 7227 cpu, go to this link  on Pdadb.net and click on "Browse all device based on MSM7227" button. Aspen cpu do support Android, and if some geek come out with Android ROM for Sony Ericsson Aspen, don't feel surprise!

By the way, I not sure whether Aspen cpu do support Windows Phone 7 OS, but I don't think there will be upgrade for Aspen from SE. If you like to get a device with WP7, get a new phone. :)


Fyi, Qualcomm MSM7227 supported Google Android 1.6 and 2.1.

Understand More On History of CPU

The "History of Overclocking" from Atomicmpc.com.au is pretty good resource to understand history of CPU back to 80386 and 80486. The article did included background of obsolete CPU company like Cyrix.

History of Overclocking Part One

History of Overclocking Part Two

The K6 has an interesting history – unsatisfied by its own designs, AMD purchased a company called NexGen, that was developing a chip called the Nx686 at the time. As a result AMD got access to Vinod Dahm, the designer of the original Pentium who had moved to NexGen. AMD changed the design so it would fit Socket 7, included MMX support, and shipped the result. Eventually the PR ratings AMD used were dropped when it started matching the actual MHz of the CPUs. The last ever K6 used Super Socket 7, giving it access to a 100MHz bus. This is the first time AMD used a different socket to Intel, even though it was backwards compatible with other Socket 7 chips. It was a stop-gap solution to up the FSB while AMD was designing Slot A, as it no longer had rights to Intel’s sockets. This worked to AMD’s advantage – those who invested in a Super Socket 7 board had compatibility with both the upcoming K6-2 and K6-III.

Cyrix does get a mention in our little history for implementing the 75MHz bus on its 6x86 and 6x86MX processors. This meant the PCI bus ran at 37.5MHz, which caused problems with some add-in cards. Cyrix caused even more problems in 1998 when it upped the speed of its MII chip to 83MHz, forcing a completely unreasonable 41.5MHz on PCI. As a result things were unstable, particularly IDE controllers.

CPU Wars Part 1: General Trends

Informit.com has a series article on CPU Wars that talking about the real competition between CPU manufacturers and general trends in the CPU industry. Worth to spend some time to read through it (note: a long article), a lot of technical stuff in the article and you may gain something for your computer knowledge on CISC and RISC.

Article links:
CPU Wars Part 1

Early RISC designs had very few instructions. Most omitted even multiply and add instructions, since these operations could be implemented using a combination of adds and shifts. This turned out not to be such a great idea. The minimum amount of time in which an instruction can complete is one cycle, and chips with divide instructions eventually were able to complete them in fewer instructions than a chip that executed the shifts and adds, especially on floating-point values, where extra normalization steps are required and the mantissa and exponent must be handled separately.

Intel’s x86 architecture is the last surviving CISC chip, and has a particularly baroque architecture, including things like string-comparison instructions. All x86 CPUs since the Pentium have contained a more RISC-y core and have translated these instructions into sequences of μops that are executed internally. Starting with the Core microarchitecture, Intel has done this in reverse, reassembling sequences of μops into sequences that can be executed with a single instruction.

The only real difference between a RISC and a CISC chip these days is the public instruction set; the internal instruction sets are likely to be similar. RISC and CISC are not the only possible alternatives, however. RISC came from a desire to simplify the core, and a group at Yale in the early 1980s worked out that you could take this design even further. A pipelined CPU has to do a lot of work to determine which instructions can be executed concurrently.